1. Field of the Invention
The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus for preventing an inverse current from being introduced from a panel to a panel driver to reduce a heat dissipation of a data driving integrated circuit, thereby improving a driving reliability.
2. Description of the Background Art
Plasma display apparatus displays an image by exciting and emitting a phosphor using ultraviolet rays generated when an inert mixture gas is discharged. In the plasma display apparatus, thinning and large-sizing are not only easy but also a quality of picture is improved owing to a recent development of technology.
FIG. 1 illustrates a method for expressing the gray level in the plasma display apparatus. In order to embody the gray level of the image, the plasma display apparatus is time-division driven with one frame divided into several subfields having a different number of times of emission.
Each subfield is divided into a reset period for initializing a whole screen, an address period for selecting a scan line and selecting a discharge cell at the selected scan line, and a sustain period for embodying the gray level depending on the number of times of discharge.
For example, when the image is displayed at 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields (SF1 to SF8) as in FIG. 1.
Each of the eight subfields (SF1 to SF8) is divided into the reset period, the address period, and the sustain period as described above.
The reset period and the address period of each subfield are the same at each subfield whereas the sustain period and the number of sustain pulses allocated to the sustain period are increased at a rate of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) at each subfield.
Accordingly, the plasma display apparatus accumulates brightness of each subfield, and displays the image at a desired gray level.
FIG. 2 schematically illustrates an electrode arrangement of a conventional three-electrode alternating current surface discharge type plasma display apparatus.
Referring to FIG. 2, the conventional three-electrode alternating current surface discharge type plasma display apparatus includes scan electrodes (Y1 to Yn) and a sustain electrode (Z) formed at an upper substrate, and address electrodes (X1 to Xm) formed at a lower substrate to intersect with the scan electrodes (Y1 to Yn) and the sustain electrode (Z).
Discharge cells 1 are arranged in matrix at intersections of the scan electrodes (Y1 to Yn), the sustain electrode (Z), and the address electrodes (X1 to Xm).
A dielectric layer and an MgO protective layer (not shown) are layered on the upper substrate where the scan electrodes (Y1 to Yn) and the sustain electrode (Z) are formed.
A barrier rib for preventing optical and electrical jamming between adjacent discharge cells 1 is formed on the lower substrate where the address electrodes (X1 to Xm) are formed.
The phosphor excited by the ultraviolet rays and emitting visible rays is formed at the lower substrate and a surface of the barrier rib.
The inert mixture gas, such as He+Xe, Ne+Xe, and He+Xe+Ne, is injected into a discharge space between the upper substrate and the lower substrate.
FIG. 3 illustrates a driving waveform applied to the conventional plasma display apparatus of FIG. 2.
Referring to FIG. 3, each of the subfields (SFn-1 and SFn) includes the reset period (RP) for initializing the discharge cells 1 of the whole screen, the address period (AP) for selecting the discharge cell, the sustain period (SP) for sustaining the discharge of the selected discharge cell 1, and an erasure period (EP) for erasing wall charges within the discharge cell 1.
In the erasure period (EP) of the (n-1)th sub field (SFn-1), an erasure ramp waveform (ERR) is applied to the sustain electrode (Z). During the erasure period (EP), 0V is applied to the scan electrode (Y) and the address electrode (X). The erasure ramp waveform (ERR) is a positive ramp waveform that gradually increases from OV to a positive sustain voltage (Vs). By the erasure ramp waveform (ERR), erasure discharge occurs between the scan electrode (Y) and the sustain electrode (Z) within on-cells where the sustain discharge occurs.
In a setup period (SU) of the reset period (RP) at which the nth subfield (SFn) initiates, a positive ramp waveform (PR) is applied to all the scan electrodes (Y), and 0V is applied to the sustain electrode (Z) and the address electrode (X).
By the positive ramp waveform (PR) of the setup period (SU), a voltage of the scan electrode (Y) gradually increases from a positive sustain voltage (Vs) to a reset voltage (Vr) higher than the positive sustain voltage.
By the positive ramp waveform (PR), a dark discharge not almost generating light is generated between the scan electrode (Y) and the address electrode (X) within the discharge cells of a whole screen, and at the same time, the dark discharge is generated even between the scan electrode (Y) and the sustain electrode (Z).
As a result of the dark discharge, soon after the setup period (SU), positive wall charges remain on the address electrode (X) and the sustain electrode (Z), and negative wall charges remain on the scan electrode (Y).
While the dark discharge is generated in the setup period (SU), a gap voltage (Vg) between the scan electrode (Y) and the sustain electrode (Z) and a gap voltage between the scan electrode (Y) and the address electrode (X) are initialized to a voltage close to a firing voltage (Vf) capable of generating the discharge.
Consequently to the setup period (SU), a negative ramp waveform (NR) is applied to the scan electrode (Y) in the setdown period (SD) of the reset period (RP).
At the same time, the positive sustain voltage (Vs) is applied to the sustain electrode (Z), and OV is applied to the address electrode (X).
By the negative ramp waveform (NR), the voltage of the scan electrode (Y) gradually decreases from the positive sustain voltage (Vs) to a negative erasure voltage (Ve).
By the negative ramp waveform (NR), the dark discharge is generated between the scan electrode (Y) and the address electrode (X) within the discharge cell of the whole screen and at the same time, the dark discharge is generated even between the scan electrode (Y) and the sustain electrode (Z).
As a result of the dark discharge of the setdown period (SD), a distribution of the wall charges within the respective discharge cells 1 is changed to addressable condition.
At this time, excessive wall charges unnecessary for an address discharge are erased from and a predetermine amount of wall charges remains on the scan electrode (Y) and the address electrode (X) within the respective discharge cells 1. While the negative wall charges are moved from the scan electrode (Y) and accumulated on the sustain electrode (Z), the wall charges on the sustain electrode (Z) are inverted from a positive polarity to a negative polarity. While the dark discharge is generated in the setdown period (SD) of the reset period (RP), a gap voltage between the scan electrode (Y) and the sustain electrode (Z) and a gap voltage between the scan electrode (Y) and the address electrode (X) gets close to the firing voltage (Vf).
In the address period (AP), a negative scan pulse (−SCNP) is sequentially applied to the scan electrode (Y) and at the same time, a positive data pulse (DP) is applied to the address electrode (X) in synchronization with the scan pulse (−SCNP). A voltage of the scan pulse (−SCNP) is a scan pulse (Vsc) decreasing from OV or the negative scan bias voltage (Vyb) close to OV to the negative scan voltage (−Vy). A voltage of the data pulse (DP) is the positive data voltage (Va).
During the address period (AP), the positive Z bias voltage (Vzb) lower than the positive sustain voltage (Vs) is supplied to the sustain electrode (Z). Soon after the reset period (RP), in a state where the gap voltage is adjusted to be close to the firing voltage (Vf), the gap voltage between the scan electrode (Y) and the address electrode (X) exceeds the firing voltage (Vf) within the on-cells to which the scan voltage (Vsc) and the data voltage (Va) are applied while generating a primary address discharge between the electrodes (X and Y).
The primary address discharge between the scan electrode (Y) and the address electrode (X) occurs near an edge distant from a gap between the scan electrode (Y) and the sustain electrode (Z). The primary address discharge generates priming charged particles within the discharge cell, and induces a second discharge between the scan electrode (Y) and the sustain electrode (Z).
Meantime, a distribution of wall charges within off-cells not generating the address discharge is substantially identical with the distribution of wall charges soon after the setdown period.
In the sustain period (SP), the sustain pulses (SUSP) of the positive sustain voltage (Vs) are alternately applied to the scan electrode (Y) and the sustain electrode (Z). If so, in the on-cells selected by the address discharge, the sustain discharge occurs between the scan electrode (Y) and the sustain electrode (Z) at each sustain pulse (SUSP).
On contrary, in the off-cells, the discharge does not occur during the sustain period. This is because, since the distribution of wall charges of the off-cells are substantially identical with the distribution of wall charges soon after the setdown period, when the positive sustain voltage (Vs) is initially applied, the gap voltage between the scan electrode (Y) and the sustain electrode (Z) cannot exceed the firing voltage (Vf).
However, the conventional plasma display apparatus has a drawback in that a data driving integrated circuit for supplying data to the address electrode dissipates a large amount of heat and frequently fails. This phenomenon results in the greatest high current introduced from the address electrode (X) to the data driving integrated circuit. This will be in detail described with reference to FIG. 4.
FIG. 4 is an equivalent circuit diagram illustrating conventional data driving integrated circuit and plasma display panel connected thereto.
Referring to FIG. 4, the data driving integrated circuit 40 includes a first switching element (S1) connected to a data voltage source (Va); and a second switching element (S2) connected to a base voltage source (GND). The data driving integrated circuit 40 includes an energy recovery circuit (not shown) for charging the address electrode (X) by a RC series circuit, and recovering reactive power not contributing to the discharge from the address electrode (X). In general, the data driving integrated circuit 40 is connected to the plurality of address electrodes (X) provided to the plasma display apparatus in the COF form.
In FIG. 4, “Rp” denotes a parasitic resistance of the address electrode (X) provided between the data driving integrated circuit and the panel capacitor (Cp), and the panel capacitor (Cp) denotes a parasitic capacitance between the address electrode (X) and the scan electrode (Y), and a parasitic capacitance between the address electrode (X) and the sustain electrode (Z).
During the address period, when data is at a high logic level, the first switching element (S1) turns on under the control of the timing controller and supplies a data voltage (Va) of more than about 80V to the address electrode (X) whereas, when the data is at a low logic level, turns off under the control of the timing controller. The first switching element (S1) maintains an off state during a period besides the address period.
During the address period, when the data is at the low logic level, the second switching element (S2) turns on under the control of the timing controller and supplies the base voltage (GND) to the address electrode (X) whereas, when the data is at the high logic level, turns off under the control of the timing controller. The second switching element (S2) maintains an on state during a period besides the address period.
The data driving integrated circuit 40 has a drawback of dissipating the heat by the inverse current introduced from the panel capacitor (Cp) via the parasitic resistance (Rp) and capable of being damaged due to dielectric breakdown, which is caused by the inverse current, of switching elements embodied by semiconductor switching elements. As an amount of data gets larger or the data voltage (Va) is higher, the inverse current more increases depending on a dielectric characteristic of the panel.